Bandgap voltage reference circuits are well known in the art from the early 1970's as is evidenced by the IEEE publications of Robert Widlar (IEEE Journal of Solid State Circuits Vol. SC-6 No 1 Feb. 1971) and A. Paul Brokaw (IEEE Journal of Solid State Circuits Vol. SC-9 No 6 Dec. 1974).
These circuits implement configurations for the realization of a stabilized bandgap voltage. As discussed in David A. Johns and Ken Martin “Analog Integrated Circuit Design”, John Wiley & Sons, 1997, these circuits and other modifications to same are based on subtracting the voltage of a forward based diode (or base emitter junction) having a negative temperature coefficient from a voltage proportional to absolute temperature (PTAT). Typically, the PTAT voltage is formed by amplifying the voltage difference (ΔVbe) of two forward biased base-emitter junctions operating at different current densities.
An example of such a circuit is shown in schematic form in FIG. 1. In this Figure a bandgap voltage reference circuit is implemented using an operational amplifier A, three resistors, P1, P2 and R3, and two parasitic transistors, Q1 and Q2, with Q2 having an emitter area n times larger than Q1. The output of the amplifier A is coupled to its inverting terminal via the feedback resistor R3. The output of A is also coupled to the emitter of transistor Q1 via the resistor R1, with the base of Q1 being tied to ground. The inverting terminal of A is coupled to the emitter of Q2 via the resistor R2, with the base of Q2 also tied to ground. The non-inverting terminal of A is coupled to the emitter of Q1.
It is well known that the difference in base-emitter voltages of two bipolar transistors operating at different collector current densities is proportional to absolute temperature. In FIG. 1 making the emitter area of Q2 “n” times larger than emitter area of Q1 ensures the difference in collector current densities. As the amplifier A keeps the two inputs, noninverting, (+) and inverting, (−), substantially at the same voltage level the voltage developed across R2 is:ΔVBE=(kT/q)ln(nI1/I2)  (1)
It is known and can be shown quite easily that the reference voltage is equal to ΔVBE multiplied by a factor of K and added to the base emitter voltage of the junction with the larger current density, as is shown in Equation 2Vref=VBE1+KΔVBE,  (2)
For the circuit of FIG. 1 the reference voltage is:Vref=VBE1+(R3/R2)kT/q(ln(nR3/R1)  (3).
This equation, it will be understood can be used to determine the theoretical reference voltage for specific situations and implementations.
In other implementations current mirrors may replace the resistors R1 and R3 of FIG. 1. FIG. 2 shows an example of such a modification. The circuit of FIG. 2 is similar to that of FIG. 1, with the same components being given the same reference numerals. In the circuit of FIG. 2, the non-inverting terminal of the operational amplifier A is connected to the emitter of Q2 via the resistor R2. The inverting terminal is connected to the emitter of Q1. The base of both Q1 and Q2 are connected to ground. The output of A is coupled to the gates of PMOS devices M1 and M2, rather than the resistors R1 and R3 of FIG. 1. The source terminals of M1 and M2 must then be connected to the power supply, referenced in the figure as VDD. The drain of M2 is connected to the non-inverting terminal of amplifier A.
One important specification of any bandgap voltage reference is minimum supply voltage. As is well known, if the amplifier A (FIG. 1 and FIG. 2) has a differential stage which uses a pair of PMOS transistors, the common input voltage (the term “common input voltage” being used herein synonymously with “common mode input voltage” and “input common mode voltage”) is lower as compared to that provided by an NMOS input pair. However, a differential pair of PMOS transistors is preferred due to noise consideration. For the case of a PMOS input pair the threshold voltage of the PMOS transistors and the input common mode voltage of the amplifier determine the minimum supply voltage. As the threshold voltage for a specific process is given, the only way to reduce minimum supply voltage is to reduce the common input voltage of the amplifier, i.e. the base-emitter voltage for the circuits of FIG. 1 and FIG. 2.
Methods of resistive subdivision are well known such as those described in Fa Nang Leung et al., “A sub-1-V 15-ppm, C CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device”, IEEE Journal Solid State Circuit, Vol.37/4, pp.526-530, April 2002. The basic configuration of these methods is shown in FIG. 3. The circuit of FIG. 3 has two resistor dividers, one connected to each or the input terminals of the amplifier A. Resistors R2B1 and R2B2 act as a resistor divider for the inverting terminal of amplifier A, with the voltage of the inverting terminal being taken between R2B1 and R2B2 as shown. Similarly, resistors R2A1 and R2A2 act as a resistor divider for the non-inverting terminal of amplifier A, with the voltage of the non-inverting terminal being taken between R2A1 and R2A1 as shown. In this circuit, the output of the amplifier A is connected to the gates of PMOS devices M1, M2 and M3, in the same manner as that of FIG. 2, with their sources being driven by the supply voltage VDD. The drain of M2 is connected to the emitter of Q1, and also to the resistor P2B1. The drain of M1 is connected both to the emitter of Q2 via resistor R1, and to resistor R2A1. The emitter area of Q2 is n times larger than Q1, as in the previous figures. The drain of M3 is coupled to ground via a resistor R3. The resistors R2A2 and R2B2 and the base of both Q1 and Q2 are all tied to the same reference potential, shown as ground in the schematic diagram of FIG. 3.
Using these configurations, the base-emitter voltage of the bipolar transistor operating at high current density (Q1) is subdivided by R2B1 and R2B2. The second bipolar transistor Q2 operating at low current density (Q2) and R1 generates a PTAT voltage across R1 if the ratio of second resistive divider, R2A1 and R2A2, is the same as the first resistive divider. One of the main disadvantages of this configuration is that the offset and noise of the amplifier A are amplified by the subdivision ratio. As a result, as the common voltage of the amplifier A reduces, the output offset and noise increases.
Another configuration allowing low voltage operating is described in U.S. Pat. No. 6,307,426 of Giulio Ricotti et al. The basic idea of this configuration is to introduce an offset into the input bipolar differential stage of an amplifier. This offset voltage is a typical PTAT voltage. The reference voltage with low temperature coefficient is obtained by adding this PTAT voltage to a scaled CTAT voltage. The main drawbacks of this configuration are:                1) It can not be implemented in a CMOS process where only pure lateral transistors having all three terminals are available;        2) In a typical bipolar process there is also another unavoidable offset which is added to the PTAT offset voltage. As a result the real PTAT voltage and the output voltage may have a large spread from device to device and from lot to lot.        
There is therefore a need to provide a circuitry that can provide a voltage bandgap reference signal, which can be implemented in CMOS technology and which provides for improved headroom over traditional circuitry.
There is also a need for a circuit that provides for reduced spread yet can be implemented in circuits with low availability of headroom.